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features ? ? ? l o w noise - less than 15 m v p-p ? l o w p o wer dissipation - description ar e hig h per f o r manc e , l o w power, 3 1 / 2 digit a/d converters. included are seven seg- ment decoders, display d rivers, a reference, and a clock. i s designe d t o inter f ac e wit h a liqui d c r ysta l dis- play (lcd) and includes a multiplexed backplane drive; the 710 7 wil l directl y d r i v e a n inst r umen t si z e ligh t emitting diode (led) display. 710 7 b r in g togethe r a combinatio n of hig h accu r ac y , v ersatilit y , an d t r u e econo m y . or dering inf ormation part no. temp. range ( o c) package pkg. no. 13 1 2 3 4 5 6 7 8 9 10 11 12 14 15 16 17 18 19 20 v+ d1 c1 b1 a1 f1 g1 e1 d2 c2 b2 a2 f2 e2 d3 b3 f3 e3 (1000) ab4 pol 28 40 39 38 37 36 35 34 33 32 31 30 29 27 26 25 24 23 22 21 osc 1 osc 2 osc 3 test ref hi ref lo c ref + c ref - common in hi in lo a-z buff int v- g2 (10 s) c3 a3 g3 bp/gnd (1 s) (10 s) (100 s) (minus) (100 s) wing shing computer components co., (h.k.)ltd. tel:(852)2341 9276 fax:(852)2797 8153 homepage: http://www.wingshing.com e-mail: wsccltd@hkstar.com
absolute maximum ratings thermal information supply voltage thermal resistance (typical, note 2) ja ( /w) ws7106, v+ to v-???????????.15v pdip package?????????????????. ?? ???? 50 ws7107, v+ to gnd????????.??6v maximum junction temperature??????????????.. ???150 ws7107, v_ to gnd????????. ?.-9v maximum storage temperature range???????.???..-65 to 150 analog input voltage (either input) (note 1)v+ to v- reference input voltage (either input)v+ to v- clock input ws7106test to v+ ws7107gnd to v+ operating conditions temperature range??????????0 to 70 caution: stresses above those listed in ?absolute maximum ratings? may cause permanent damage to the device. this is a stress o nly rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not i mplied. notes: 1. input voltages may exceed the supply voltages provided the input current is limited to 100a 2. ja is measured with the component mounted on an evaluation pc on board in fee air. electrical specifications (note 3) parameter test conditions min typ max unit system performace zero input reading v in =0.0v, full scale = 200mv -000.0 000.0 +000.0 digital reading ratiometric reading v in = v ref , v ref = 100mv 999 999/1000 1000 digital reading rollover error -v in =+v in =200mv difference in reading for equal positive and negative inputs near full scale -1 0.2 +1 counts linearity full scale = 200mv or full scale = 2v maximum deviation from best straight line fit (note 6) -1 0.2 +1 counts common mode rejection ratio v cm = 1v, v in = 0v, full scale = 200mv(note 6) - 50 - v/v end power supply character v+ supply current v in = 0 (does not include led current for ws7107 - 0.5 1.8 ma end power supply character v- supply current ws7107 only - 0.5 1.8 ma common pin analog common voltage 25k ? between common and positive supply (with respect to + supply) 2.4 3 .0 3.2 v noise (p k -p k value not exceeded 95% of time) v in =0v full scale=200mv 15 uv p-p input leakage current v in =0v 1 10 pa analog common temperature coefficient 25k between common and v+ 0 -70 60 75 ppm/ scale factor temperature coefficient v in =199mv 0 -70 ext. ref. 0ppm/ 60 75 ppm/ zero reading drift v in =0 v-70 0.2 1 uv/ di s p l a y dr i ver w s 7106 o n l y peak-to-peak segment drive voltage peak-to-peak backplane drive voltage v+ = to v- = 9v (note 5) 4 5 6 v
t ypical applications and t est cir cuits segment sinking current v+ = 5v, segment voltage = 3v (except pins 19 and 20) 58 - ma pin 19 only 10 16 - m a pin 20 only 47 - ma notes: 3 . dissipation rating assumes device is mounted with all leads soldered to printed circuit board. electrical speci?cation s (conti n ued) parameter test conditions min typ max unit 710 6 tes t circui t an d typica l applic a tio n wit h lc d displ a y component s selecte d fo r 200mv full scale 710 7 tes t circui t an d typica l applic a tio n wit h le d displ a y component s selecte d fo r 200mv full scale 13 1 2 3 4 5 6 7 8 9 10 11 12 14 15 16 17 18 19 20 28 40 39 38 37 36 35 34 33 32 31 30 29 27 26 25 24 23 22 21 v+ d1 c1 b1 a1 f1 g1 e1 d2 c2 b2 a2 f2 e2 d3 b3 f3 e3 ab4 pol osc 1 osc 2 osc 3 test ref hi ref lo c ref + c ref - com in hi in lo a-z buff int v- g2 c3 a3 g3 bp display display c 1 c 2 c 3 c 4 r 3 r 1 r 4 c 5 + - in r 5 r 2 9v c 1 = 0.1 m f c 2 = 0.47 m f c 3 = 0.22 m f c 4 = 100pf c 5 = 0.02 m f r 1 = 24k w r 2 = 47k w r 3 = 100k w r 4 = 1k w r 5 = 1m w + - 13 1 2 3 4 5 6 7 8 9 10 11 12 14 15 16 17 18 19 20 28 40 39 38 37 36 35 34 33 32 31 30 29 27 26 25 24 23 22 21 v+ d1 c1 b1 a1 f1 g1 e1 d2 c2 b2 a2 f2 e2 d3 b3 f3 e3 ab4 pol osc 1 osc 2 osc 3 test ref hi ref lo c ref + c ref - com in hi in lo a-z buff int v- g2 c3 a3 g3 gnd display display c 1 c 2 c 3 c 4 r 3 r 1 r 4 c 5 + - in r 5 r 2 +5v -5v c 1 = 0.1 m f c 2 = 0.47 m f c 3 = 0.22 m f c 4 = 100pf c 5 = 0.02 m f r 1 = 24k w r 2 = 47k w r 3 = 100k w r 4 = 1k w r 5 = 1m w
t ypical integrator ampli?er output w a vef orm (int pin) design inf ormation summar y sheet ? oscillator frequency f osc = 0.45/rc c osc > 50pf; r osc > 50k w f osc (typ) = 48khz ? oscillator period t osc = rc/0.45 ? integration clock frequency f clock = f osc /4 ? integration period t int = 1000 x (4/f osc ) ? 60/50hz rejection criterion t int /t 60hz or t lnt /t 60hz = integer ? optimum integration current i int = 4 m a ? full scale analog input voltage v lnfs (typ) = 200mv or 2v ? integrate resistor ? integrate capacitor ? integrator output voltage swing ?v int maximum swing: (v- + 0.5v) < v int < (v+ - 0.5v), v int (typ) = 2v ? display count ? conversion cycle t cyc = t cl0ck x 4000 t cyc = t osc x 16,000 when f osc = 48khz; t cyc = 333ms ? common mode input voltage (v- + 1v) < v ln < (v+ - 0.5v) ? auto-zero capacitor 0.01 m f < c az < 1 m f ? reference capacitor 0.1 m f < c ref < 1 m f ?v com biased between vi and v-. ? v com @ v+ - 2.8v regulation lost when v+ to v- < @ 6.8v if v com is externally pulled down to (v+ to v-)/2, the v com circuit will turn off. 7106 p o wer supp l y : single 9v v+ - v- = 9v digital supply is generated internally v gnd @ v+ - 4.5v ? type: direct drive with digital logic supply amplitude. ? v+ = +5v to gnd v- = -5v to gnd digital logic and led driver supply v+ to gnd ? type: non-multiplexed common anode r int v infs i int ---------------- -= c int t int () i int () v int -------------------------------- = v int t int () i int () c int -------------------------------- = count 1000 v in v ref --------------- = auto zero phase (counts) 2999 - 1000 signal integrate phase fixed 1000 counts de-integrate phase 0 - 1999 counts total conversion time = 4000 x t clock = 16,000 x t osc
detailed description analog section figur e 3 sh o w s th e analo g sectio n f o r th e 7107 . eac h measuremen t cycl e i s divide d int o three phases. they are (1) auto-zero (a-z), (2) signal integrate (int) and (3) de-integrate (de). auto-zer o phase during auto-zero three things happen. first, input high and low are disconnected from the pins and internally shorted to analog common. second, the reference capacitor is charged to the reference voltage. third, a feedback loop is closed around the system to charge the auto-zero capacitor c az to compensate for offset voltages in the buffer ampli?er, integrator, and comparator. since the comparator is included in the loop, the a-z accuracy is limited only by the noise of the system. in any case, the offset referred to the input is less than 10 m v. signal integrate phase during signal integrate, the auto-zero loop is opened, the internal short i s removed, and the internal input high and low are connected to the external pins. the converter then integrates the differential voltage between in hi and in lo for a ?xed time. this differential voltage can be within a wide common mode range: up to 1v from either supply. i f, on the other hand, the input signal has no return with respect to the converter power supply, i n l o can be tied to analog common to establish the correct common mode voltage. a t the end of this phase, the polarity of the integrated signal is determined. de-integrate phase the ?nal phase is de-integrate, o r reference integrate. input low i s internally connected to analog common and input high is connected across the previously charged reference capacitor. circuitry within the chip ensures that the capacitor will be connected with the correct polarity to cause the integrator output to return t o zero. the time required for the output to return t o zero is proportional to the input signal. speci?cally the digital reading displayed is: . differential input the input can accept differential voltages anywhere within the common mode range of the input amplifier, o r specifically from 0.5v below the positive supply to 1v above the negative sup- ply. i n this range, the system has a cmrr of 86db typical. however, care must be exercised to assure the integrator out- put does not saturate. a worst case condition would be a large positive common mode voltage with a near full scale negative differential input voltage. the negative input signal drives the integrator positive when most of its swing has been used up by the positive common mode voltage. for these critical appli- cations the integrator output swing can be reduced to less than the recommended 2v full scale swing with little loss of accuracy. the integrator output can swing to within 0.3v of either supply without loss of linearity. display count = 1000 v in v ref --------------- ? ? ?? figure 3 . analog section of de - de+ c int c az r int buffer a-z int - + a-z comparator in hi common in lo 31 32 30 de- de+ int a-z 34 c ref + 36 ref hi c ref ref lo 35 a-z a-z 33 c ref - 28 29 27 to digital section a-z and de () integrator int stray stray v+ 10 m a v- n input high 2.8v 6.2v v+ 1 input low - + - + - +
differential reference the reference voltage can be generated anywhere within the power supply voltage of the converter. the main source of com- mon mode error is a roll-over voltage caused by the reference capacitor losing or gaining charge to stray capacity on its nodes. i f there is a large common mode voltage, the reference capacitor can gain charge (increase voltage) when called up to de-integrate a positive signal but lose charge (decrease volt- age) when called up to de-integrate a negative input signal. this difference in reference for positive o r negative input voltage will give a roll-over error. h owever, by selecting the reference capacitor such that it is large enough in comparison to the stray capacitance, this error can be held to less than 0.5 count worst case. (see component value selection.) analog common this pin is included primarily to set the common mode v oltag e f o r batte r y ope r atio n where the input signals are ?oating with respect to the power supply. the common pin sets a voltage that is approxi- mately 2.8v more negative than the positive supply. this is selected to give a minimum end-of-life battery voltage of about 6v. h owever, analog common has some of the attributes of a reference voltage. when the total supply voltage is large enough to cause the zener to regulate (>7v), the common voltage will have a l ow voltage coef?cient (0.001%/v), low output impedance ( @ 15 w ), and a temperature coef?cient typically less than 80ppm/ o c. the limitations of the on chip reference should also be recogni z ed , h o w e v e r . wit h th e which results from the led drivers can cause some degradation in performance. due to their higher thermal resis- tance, plastic parts are poorer in this respect than ceramic. the combination of reference temperature coefficient (tc), internal chip dissipation, and package thermal resistance can increase noise near full scale from 25 m vto80 m v p-p . also the linearity in going from a high dissipation count such as 1000 (20 segments on) to a l ow dissipation count such as 1111(8 segments on) can suffer by a count or more. d evices with a positive t c reference may require several counts to pull out of an over-range condition. this is because over-range is a l ow dissipation mode, with the three least significant digits blanked. similarly, units with a negative t c m ay cycle between over-range and a non-over-range count as the die alternately heats and cools. all these problems are of course eliminated if an external reference is used. 7106 , wit h it s negligi b l e dissipation , suf f er s from none of these problems. i n either case, a n external reference can easily be added, as shown in figure 4. analog common is also used as the input low return during auto-zero and de-integrate. i f i n l o i s different from analog common, a common mode voltage exists in the system and is taken care of by the excellent cmrr of the converter. however, in some applications in lo will be set at a ? xed known voltage (power supply common for instance). in this application, analog common should be tied to the same point, thus removing the common mode voltage from the converter. the same holds true for the reference voltage. i f reference can be conveniently tied to analog common, it should be since this removes the common mode voltage from the reference system. within the lc, analog common is tied to an n-channel fet that can sink approximately 30ma of current to hold the voltage 2.8v below the positive supply (when a load is trying to pull the common line positive). however, there is only 10 m a o f source current, so common may easily be tied to a more negative voltage thus overriding the internal reference. test th e tes t pi n se r v e s t w o function s . o n th e coupled to the internally generated digital supply through a 500 w resistor. thus it can be used as the negative supply for externally generated segment drivers such as decimal points or any other presentation the user may want to include on the lcd display. figures 5 and 6 show such an application. no more than a 1ma load should be applied. figure 4a. figure 4b. figure 4. using an external reference v ref lo ref hi v+ v- 6.8v zener i z v ref hi ref lo common v+ icl8069 1.2v reference 6.8k w 20k w v+ bp test 21 37 to lcd backplane to lcd decimal point 1m w figure 5. simple inverter for fixed decimal point
the second function is a lamp test. when test is pulled high (to v+) all segments will be turned on and the display should read 1888. the test pin will sink about 15ma under these conditions. ca ution: in the lamp test mode , the segments ha v e a constant dc v oltage (no square-w a v e). this ma y b ur n the lcd displa y i f main- tained f or e xtended per iods . digital section figure s 7 an d 8 sh o w th e digita l sectio n f o r th e , a n inte r na l digital ground is generated from a 6 v zener diode and a large p-channel source follower. this supply is made stiff to absorb the relative large capacitive currents when the back plane (bp) voltage is switched. the bp frequency is the clock frequency divided by 800. for three readings/sec., this is a 60hz square wave with a nominal amplitude of 5v. the segments are driven at the same frequency and amplitude and are in phase with bp when off, but out of phase when on. in all cases negligible dc voltage exists across the segments. figur e 8 i s th e digita l sectio n o f th e 710 6 e xcep t tha t th e regulate d suppl y an d ba c k plane drive h ave been eliminated and the segment drive has been increased from 2ma to 8ma, typical for instrument size common anode led displays. since the 1000 output (pin 19) must sink current from two led segments, i t has twice the drive capability or 16ma. in both devices, the polarity indication is on for negative analog inputs. i f i n l o and in hi are reversed, this indication can be reversed also, if desired. v+ bp test decimal point select cd4030 gnd v+ to lcd decimal points figure 6. exclusive or gate for decimal point drive 7 segment decode segment output 0.5ma 2ma internal digital ground typical segment output v+ lcd phase driver latch 7 segment decode ? 200 logic control internal v th = 1v 7 segment decode 1000s 100s 10s 1 s to switch drivers from comparator output digital ground ? 4 clock 40 39 38 osc 1 osc 2 osc 3 backplane 21 v+ test v- 500 w 37 26 6.2v counter counter counter counter 1 c a b c d f g e a b a b c d f g e a b c d f g e ? ? three inverters one inverter shown for clarity 7106 digital section
system timing figur e 9 sh o w s th e clo c kin g ar r angemen t use d i n the . t w o basi c clo c kin g ar r angements can be used: 1. figure 9a. an external oscillator connected to pin 40. 2. figure 9b. an r-c oscillator using all three pins. the oscillator frequency is divided by four before it clocks the decade counters. i t i s then further divided to form the three convert-cycle phases. these are signal integrate (1000 counts), reference de-integrate (0 to 2000 counts) and auto-zero (1000 to 3000 counts). for signals less than full scale, auto-zero gets the unused portion of reference de-integrate. this makes a complete measure cycle of 4,000 counts (16,000 clock pulses) independent of input voltage. for three readings/second, an oscillator frequency of 48khz would be used. to achieve maximum rejection of 60hz pickup, the signal integrate cycle should be a multiple of 60hz. oscillator frequencies of 240khz, 120khz, 80khz, 60khz, 48khz, 40khz, 33 1 / 3 khz, etc. should be selected. for 50hz rejec- tion, oscillator frequencies of 200khz, 100khz, 66 2 / 3 khz, 50khz, 40khz, etc. would be suitable. note that 40khz (2.5 readings/second) will reject both 50hz and 60hz (also 400hz and 440hz). 7 segment decode to segment 0.5ma 8ma digital ground typical segment output v+ latch 7 segment decode logic control 7 segment decode 1000s 100s 10s 1 s to switch drivers from comparator output digital ground ? 4 clock 40 39 38 osc 1 osc 2 osc 3 v+ test 500 w counter counter counter counter 1 v+ 37 27 c a b c d f g e a b a b c d f g e a b c d f g e ? ? three inverters one inverter shown for clarity 7107 digital section clock internal to part 40 39 38 gnd ? 4 clock internal to part 40 39 38 ? 4 rc oscillator r c test figure 9b. figure 9. clock circuits figure 9a.
component v alue selection integrating resistor both the buffer ampli?er and the integrator have a class a output stage with 100 m a o f quiescent current. they can supply 4 m a o f d rive current with negligible nonlinearity. the integrating resistor should be large enough to remain in this very linear region over the input voltage range, but small enough that undue leakage requirements are not placed on the pc board. for 2 v full scale, 470k w is near optimum and similarly a 47k w for a 200mv scale. integrating capacitor the integrating capacitor should be selected to give the maximum voltage swing that ensures tolerance buildup will not saturate the integrator swing (approximately. 0.3v from eithe r supply) . i n th e analog common is used as a reference, a nominal +2v full- scal e inte g r ato r s win g i s ?n e . f o r th e supplies and analog common tied to supply ground, a 3.5v to +4v swing is nominal. for three readings/second (48khz clock) nominal values for c lnt are 0.22 m f and 0.10 m f, respectively. o f course, i f different oscillator frequen- cies are used, these values should be changed in inverse proportion to maintain the same output swing. an additional requirement of the integrating capacitor is that it must have a l ow dielectric absorption to prevent roll-over errors. while other types of capacitors are adequate for this application, polypropylene capacitors give undetectable errors at reasonable cost. auto-zero capacitor the size o f the auto-zero capacitor has some in?uence on the noise of the system. for 200mv full scale where noise is very important, a 0.47 m f capacitor is recommended. on the 2v scale, a 0.047 m f capacitor increases the speed of recov- ery from overload and is adequate for noise on this scale. reference capacitor a 0.1 m f capacitor gives good results in most applications. however, where a large common mode voltage exists (i.e., the ref lo pin is not at analog common) and a 200mv scale is used, a larger value is required to prevent roll-over error. generally 1 m f will hold the roll-over error to 0.5 count in this instance. oscillator components for all ranges of frequency a 100k w resistor is recommended and the capacitor is selected from the equation: reference voltage the analog input required to generate full scale output (2000 counts) is: v ln =2v ref . thus, for the 200mv and 2v scale, v ref should equal 100mv and 1v, respectively. h owever, i n many applications where the a/d is connected to a transducer, there will exist a scale factor other than unity between the input voltage and the digital reading. for instance, i n a weighing system, the designer might like t o have a full scale reading when the voltage from the transducer is 0.662v. instead of dividing the input down to 200mv, the designer should use the input voltage directly and select v ref = 0.341v. suitable values for integrating resistor and capacitor would be 1 20k w and 0.22 m f. this makes the system slightly quieter and also avoids a divider 710 7 wit h 5 v supplie s can accept input signals up to 4v. another advantage of this system occurs when a digital reading of zero is desired for v in 1 0. temperature and weighing systems with a variable fare are examples. this offset reading can be conveniently generated by connecting the voltage transducer between in hi and common and the variable (or ?xed) offset voltage between common and in lo. 710 7 i s designe d t o w o r k fro m 5 v supplie s . however, if a negative supply is not available, i t can be generated from the clock output with 2 diodes, 2 capacitors, and an inexpensive l c. figure 10 shows this application. see icl7660 data sheet for an alternative. in fact, in selected applications no negative supply is required. the conditions to use a single +5v supply are: 1. the input signal can be referenced to the center of the common mode range of the converter. 2. the signal is less than 1.5v. 3. an external reference is used. f 0.45 rc ----------- for 48khz clock (3 readings/sec), = c 100pf. = v+ osc 1 v- osc 2 osc 3 gnd v+ v- = 3.3v 0.047 m f 10 m f + - in914 in914 cd4009 figure 10. generating negative supply from +5v
t ypical applications 28 40 39 38 37 36 35 34 33 32 31 30 29 27 26 25 24 23 22 21 osc 1 osc 2 osc 3 test ref hi ref lo c ref c ref common in hi in lo a-z buff int v - g2 c3 a3 g3 bp 100pf to pin 1 set v ref = 100mv 0.1 m f 0.01 m f 1m w 100k w 1k w 22k w in + - 9v 47k w 0.22 m f 0.47 m f to backplane to display values shown are for 200mv full scale, 3 readings/sec., ?oating supply voltage (9v battery). + - values shown are for 200mv full scale, 3 readings/sec. in lo may be tied to either common for inputs ?oating with respect to supplies, o r gnd for single ended inputs. (see discussion under analog common.) 28 40 39 38 37 36 35 34 33 32 31 30 29 27 26 25 24 23 22 21 osc 1 osc 2 osc 3 test ref hi ref lo c ref c ref common in hi in lo a-z buff int v - g2 c3 a3 g3 gnd 100pf to pin 1 set v ref = 100mv 0.1 m f 0.01 m f 1m w 100k w 1k w 22k w in + - 47k w 0.22 m f 0.47 m f to display +5v -5v
7107 with an external b and-gap reference (1.2v type) 7107 with zener diode reference component values for 2v full scale 7107 oper a ted f r om single +5v t ypical applications (continued) 28 40 39 38 37 36 35 34 33 32 31 30 29 27 26 25 24 23 22 21 osc 1 osc 2 osc 3 test ref hi ref lo c ref c ref common in hi in lo a-z buff int v- g2 c3 a3 g3 gnd 100pf to pin 1 set v ref = 100mv 0.1 m f 0.01 m f 1m w 100k w 1k w 10k w in + 47k w 0.47 m f to display in lo is tied to supply common establishing the correct common mode voltage. i f common is not shorted to gnd, the input voltage may floa t with respect to the power supply and common acts as a pre-regulato r for the reference. i f common is shorted to gnd, the input is single ended (referred to supply gnd) and the pre-regulator is overridden. 10k w 1.2v (icl8069) v - v+ - 0.22 m f since low t c zeners have breakdown voltages ~ 6.8v, diode must be placed across the total supply (10v). as in the case of figure 14, in lo may be tied to either common or gnd. 28 40 39 38 37 36 35 34 33 32 31 30 29 27 26 25 24 23 22 21 osc 1 osc 2 osc 3 test ref hi ref lo c ref c ref common in hi in lo a-z buff int v - g2 c3 a3 g3 gnd 100pf to pin 1 set v ref = 100mv 0.1 m f 0.01 m f 1m w 100k w 1k w 100k w in + - 47k w 0.22 m f 0.47 m f to display +5v -5v 6.8v 28 40 39 38 37 36 35 34 33 32 31 30 29 27 26 25 24 23 22 21 osc 1 osc 2 osc 3 test ref hi ref lo c ref c ref common in hi in lo a-z buff int v - g2 c3 a3 g3 bp/gnd 100pf to pin 1 set v ref = 100mv 0.1 m f 0.01 m f 1m w 100k w 25k w 24k w in + - 470k w 0.22 m f 0.047 m f to display v+ v- 28 40 39 38 37 36 35 34 33 32 31 30 29 27 26 25 24 23 22 21 osc 1 osc 2 osc 3 test ref hi ref lo c ref c ref common in hi in lo a-z buff int v - g2 c3 a3 g3 gnd 100pf to pin 1 set v ref = 100mv 0.1 m f 0.01 m f 1m w 100k w 1k w 10k w in + - 47k w 0.22 m f 0.47 m f to display an external reference must be used in this application, since the voltage between v+ and v- is insuf?cient for correct operation of the internal reference. 15k w 1.2v (icl8069) +5v
710 7 measurein g r a tiometri c v alue s of quad load cell 7106 used as a digi t al centigrade thermometer figure 19. circuit for developing underrange and o verrange signal f r om figure 20. circuit for developing underrange and o verrange signals f r om t ypical applications (continued) 28 40 39 38 37 36 35 34 33 32 31 30 29 27 26 25 24 23 22 21 osc 1 osc 2 osc 3 test ref hi ref lo c ref c ref common in hi in lo a-z buff int v - g2 c3 a3 g3 gnd 100pf to pin 1 0.1 m f 100k w 0.47 m f to display the resistor values within the bridge are determined by the desired sensitivity. v+ 0.22 m f 47k w 28 40 39 38 37 36 35 34 33 32 31 30 29 27 26 25 24 23 22 21 osc 1 osc 2 osc 3 test ref hi ref lo c ref c ref common in hi in lo a-z buff int v - g2 c3 a3 g3 bp 100pf to pin 1 0.1 m f 0.01 m f 100k w 100k w 1m w 9v 47k w 0.22 m f 0.47 m f to backplane to display a silicon diode-connected transistor has a temperature coef?cient of about -2mv/ o c. calibration is achieved by placing the sensing transistor in ice water and adjusting the zeroing potentiometer for a 000.0 reading. the sensor should then be placed in boiling water and the scale-factor potentiometer adjusted for a 100.0 reading. scale factor adjust 100k w 220k w 22k w silicon npn mps 3704 or similar zero adjust 13 1 2 3 4 5 6 7 8 9 10 11 12 14 15 16 17 18 19 20 v+ d1 c1 b1 a1 f1 g1 e1 d2 c2 b2 a2 f2 e2 d3 b3 f3 e3 ab4 pol 28 40 39 38 37 36 35 34 33 32 31 30 29 27 26 25 24 23 22 21 osc 1 osc 2 osc 3 test ref hi ref lo c ref c ref common in hi in lo a-z buff int v- g2 c3 a3 g3 bp o /range u /range cd4023 or 74c10 cd4077 to logic v cc v+ to logic v- gnd o /range u /range cd4023 or 74c10 to logic v cc +5v v- 33k w the lm339 is required to ensure logic compatibility with heavy display loading. 13 1 2 3 4 5 6 7 8 9 10 11 12 14 15 16 17 18 19 20 v+ d1 c1 b1 a1 f1 g1 e1 d2 c2 b2 a2 f2 e2 d3 b3 f3 e3 ab4 pol 28 40 39 38 37 36 35 34 33 32 31 30 29 27 26 25 24 23 22 21 osc 1 osc 2 osc 3 test ref hi ref lo c ref c ref common in hi in lo a-z buff int v- g2 c3 a3 g3 bp 12k w + - + - + - + -
figure 22. display buffering for increased drive current t ypical applications (continued) 28 40 39 38 37 36 35 34 33 32 31 30 29 27 26 25 24 23 22 21 osc 1 osc 2 osc 3 test ref hi ref lo c ref c ref common in hi in lo a-z buff int v- g2 c3 a3 g3 bp 100pf to pin 1 0.1 m f 100k w 1k w 22k w 47k w 0.22 m f 0.47 m f to backplane to display test is used as a common-mode reference level to ensure compatibility with most op amps. 10 m f 9v 10 m f 470k w 1 m f 4.3k w 100pf (for optimum bandwidth) 1 m f 10k w 10k w 1n914 1 m f 0.22 m f 5 m f ca3140 2.2m w + - 100k w ac in scale factor adjust (v ref = 100mv for ac to rms) + - icl7107 130 w 130 w 130 w led segments +5v dm7407
dual-in-line plastic p a c k a g es (pdip) c l e e a c e b e c -b- e1 index 1 2 3 n/2 n area seating base plane plane -c- d1 b1 b e d d1 a a2 l a1 -a- 0.010 (0.25) c a m b s notes: 1. controlling dimensions: inch. in case of conflict between english and metric dimensions, the inch dimensions control. 2. dimensioning and tolerancing per ansi y14.5m - 1982. 3. symbols are defined in the mo series symbol list in section 2.2 of publication no. 95. 4. dimensions a, a1 and l are measured with the package seated in jedec seating plane gauge gs - 3. 5. d, d1, and e1 dimensions do not include mold flash or protrusions. mold flash or protrusions shall not exceed 0.010 inch (0.25mm). 6. e and are measured with the leads constrained to be per- pendicular to datum . 7. e b and e c are measured at the lead tips with the leads uncon- strained. e c must be zero or greater. 8. b1 maximum dimensions do not include dambar protrusions. dambar protrusions shall not exceed 0.010 inch (0.25mm). 9. n is the maximum number of terminal positions. 10. corner leads (1, n, n/2 and n/2 + 1 ) for e8.3, e16.3, e18.3, e28.3, e42.6 will have a b 1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm). e a -c- e40.6 (jedec ms-011-ac issue b) 40 lead dual-in-line plastic package symbol inches millimeters notesmin max min max a - 0.250 - 6.35 4 a1 0.015 - 0.39 - 4 a2 0.125 0.195 3.18 4.95 - b 0.014 0.022 0.356 0.558 - b1 0.030 0.070 0.77 1.77 8 c 0.008 0.015 0.204 0.381 - d 1.980 2.095 50.3 53.2 5 d1 0.005 - 0.13 - 5 e 0.600 0.625 15.24 15.87 6 e1 0.485 0.580 12.32 14.73 5 e 0.100 bsc 2.54 bsc - e a 0.600 bsc 15.24 bsc 6 e b - 0.700 - 17.78 7 l 0.115 0.200 2.93 5.08 4 n40 409

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